1. Field of the invention
The present invention relates to a clamp pulse producing circuit which is contained in a DC restoration circuit for producing clamp pulses for restoring DC components in composite video signals.
2. Description of the Background Art
In an image amplifying stage of a display monitor or the like, capacitor coupling is generally employed in an input end and hence DC components are lost from respective video signals, to change pedestal levels of the video signals. Thus, the entire image is disturbed in contrast such that the color of a portion to be in white is changed into gray, for example. In order to prevent this, DC restoration may be performed on the video signals losing the DC components, to thereby uniformalize the pedestal levels of the respective video signals. A DC restoration circuit has been generally employed in order to restore such DC components by clamp pulses.
FIG. 1 is a block diagram showing a conventional clamp pulse generator contained in a DC restoration circuit of a display monitor by Mitsubishi Denki Kabushiki Kaisha, product No. FA3415ATK, for producing the aforementioned clamp pulses.
A signal input terminal 1 receives a synchronizing signal SS, such as a horizontal synchronizing signal, included in a video signal VS shown in FIG. 2. A monostable multi vibrator 2, which is connected to the signal input terminal 1, is triggered on the trailing edge of the synchronizing signal SS inputted from the signal input terminal 1. In response to this, a clamp pulse CS rises as shown in FIG. 2. After a lapse of a period corresponding to a time constant C1.multidot.R1, where C1 represents capacitance of a capacitor C1 and R1 represents resistance of a resistor R1, of a time constant circuit 4 which is formed by the resistor R1 and the capacitor C1, the clamp pulse CS falls as shown in FIG. 2. Namely, the pulse width of the clamp pulse CS is determined by the time constant C1.multidot.R1. The clamp pulse CS is produced every cycle of the synchronizing signal SS, so that one clamp pulse CS determines the pedestal level of one cycle of the video signal VS. In general, the clamp pulse CS must be present in the back porch of a blanking period of the video signal VS, as shown in FIG. 2.
Since the pulse width of the clamp pulse CS is fixed by the time constant C1.multidot.R1, the conventional clamp pulse producing circuit of the aforementioned structure has the following problem: In general, the back porch of a blanking period of a video signal VS including a low-frequency synchronizing signal SS is long while that of a video signal VS including a high-frequency synchronizing signal SS is short. Thus, in the case of restoring DC components of video signals VS including synchronizing signals SS of various frequencies, the pulse width of a clamp pulse CS may exceed the back porch width of a blanking period of a video signal VS when a synchronizing signal SS is at a high frequency, whereby a DC component is insufficiently restored to disturb the constrast of an image.